It is frequently required to read the contents of a data bus when working with digital systems. Several current methods exist to do this. Assuming a bus width of 16 bits and a clocked system, the typical method is to use a logic analyzer having parallel inputs and a clock input. Each clock transition causes all 16 bits to be read and displayed on the logic analyzer display. The user must move all 16 logic probe inputs to the bus under investigation if the system has many data paths in order to make a measurement.
All data, addresses and control paths are stable after each clock step if the continuous clock is replaced by a single step clock. This single step method is useful in the development and repair of digital systems and can be used with the parallel logic analyzer described above. It is also possible to use a binary logic probe, DC meter or scope to detect logic levels and each bit sense is detected in sequence thereby constituting a serial approach. The advantage of a serial approach is that it is not necessary to move all 16 logic probes each time a different data path is analyzed. The disadvantage of the serial approach is that after each bit is sensed the value must be read and then written down. Only after all 16 bits are measured can the 16 bit value be hand converted into a useful hexidecimal or octal data value.